Storing an unchanging binary code in an integrated circuit

ABSTRACT

The invention concerns a circuit ( 1 ) for storing a binary code (B 1 , B 2 , , B i-1 , B i , , B n-1 , B n ) in an integrated circuit chip, comprising an input terminal ( 2 ) applying a signal (E) triggering reading of the code, output terminals ( 3   1   , 3   2   , , 3   i-1   , 3   i   , , 3   n-1   , 3   n ) for delivering said binary code, first electrical paths (P 1 , P 2 , , P i , , P n ) individually connecting said input terminal to each output terminal, each path inputting a fixed delay in the manufacture of the integrated circuit, and means ( 4, 5   1   , 5   2   , , 5   i   , , 5   n ) simultaneously integrating the binary states present in output of the electrical paths.

[0001] The present invention relates to the storage, in an integratedcircuit, of a permanent binary code. The present invention morespecifically applies to the writing, in the circuit manufacturing, of apermanent code intended to be read, upon use of the integrated circuit,to identify the circuit, or more specifically a circuit family.

[0002] An example of application of the present invention is theauthentication of an electronic element or assembly containing such anintegrated circuit (for example, a smart card with or without contacts),in transactions or information exchanges with another element (forexample, a card reading terminal). In such applications, it must beensured that the integrated circuit is authentic and is not a piratecircuit or an emulated circuit. In particular, in the field of smartcards, it is currently difficult to fight against a large scale piracyconsisting of manufacturing pirate cards (clones) identical to authenticcards, that is, integrating the same circuits made by similartechnological processes.

[0003] Among these applications, the present invention more specificallyrelates to those where a permanent code common to several circuits isdesired to be written. It may be, for example, an identifier of themanufacturer, an identifier of the original value of a prepaid countunit card (telephone unit cards), etc.

[0004] Memories or registers embedded in the integrated circuit arecurrently used to store this or these codes. The code is written in anon-modifiable manner in the storage element before or aftermanufacturing.

[0005] A disadvantage of such a technique is that it requires a visibleprogramming, making the code detectable out of the circuit operation.Indeed, whether the code written upon manufacturing or by subsequentdefinitive programming, the fuse-type elements having been used for thiswriting are then visually identifiable. The progress made in terms ofintegrated circuit optical analysis then enables piracy of the code.

[0006] Another disadvantage of such a technique is that the subsequentcircuit authentication, upon its use, requires a storage element readprocess, which takes time.

[0007] The present invention aims at providing a novel solution forstoring a binary code in an integrated circuit.

[0008] The present invention more specifically aims at enabling storageof a code which cannot be visually detected, even with high-performanceoptical detection means.

[0009] The present invention also aims at providing a solution whichprovides the stored code without requiring a memory reading typeprocedure, and in an almost instantaneous manner.

[0010] The present invention also aims at providing a solution requiringno circuit programming after manufacturing.

[0011] The present invention further aims at providing a solution whichis particularly simple to implement.

[0012] To achieve these objects, the present invention provides acircuit for storing a binary code in an integrated circuit chip,including:

[0013] an input terminal for application of a signal for triggering areading of the code;

[0014] output terminals adapted to providing said binary code;

[0015] first electric paths individually connecting said input terminalto each output terminal, each path introducing a delay set uponmanufacturing of the integrated circuit; and

[0016] means for simultaneously taking into account binary statespresent at the outputs of the electric paths.

[0017] According to an embodiment of the present invention, each firstelectric path is formed of a delay element and of a flip-flop having aninput terminal connected at the output of the corresponding delayelement and having an output terminal defining one of the outputterminals of the circuit.

[0018] According to an embodiment of the present invention, said meansfor taking into account include a second electric path introducing adelay included in the range of the delays introduced by said firstpaths, said second path being interposed between said input terminal anda terminal for triggering the taking into account of said binary states.

[0019] According to an embodiment of the present invention, the clockinputs of the different flip-flops are all connected to said triggeringterminal.

[0020] According to an embodiment of the present invention, the firstelectric paths are chosen to introduce delays which remain shorter orlonger than the delay of the second path, despite possible technologicaldispersions.

[0021] The foregoing objects, features and advantages of the presentinvention, will be discussed in detail in the following non-limitingdescription of specific embodiments in connection with the accompanyingdrawings, in which:

[0022]FIG. 1 shows an embodiment of an integrated storage circuitaccording to the present invention; and

[0023]FIGS. 2A and 2B illustrate, in the form of timing diagrams, theoperation of the identification circuit of FIG. 1, for two differentcodes.

[0024] For clarity, only those elements which are necessary to theunderstanding of the present invention have been shown in the drawingsand will be described hereafter. In particular, the destination and theexploitation of the stored binary code have not been detailed and are noobject of the present invention.

[0025] A feature of the present invention is to store a binary code bymeans of physical parameters of the actual integrated circuit. Morespecifically, the present invention provides submitting a same inputsignal (a logic signal including at least one edge) to several differentdelays coming from distinct electric paths.

[0026] Another feature of the present invention is to provide directcomparison of the delays introduced by the different paths with respectto an intermediary delay, to make the code delays insensitive totechnological and/or manufacturing process variations.

[0027]FIG. 1 shows the electric diagram of an embodiment of anintegrated storage circuit according to the present invention.

[0028] In this example, circuit 1 includes a single input terminal 2intended to receive a digital signal E for triggering a code reading.According to the present invention, signal E alone is sufficient for thecode to be provided. To implement the present invention, signal E mustinclude, as will be seen hereafter in relation with FIGS. 2A and 2B, atleast one edge per triggered reading.

[0029] Circuit 1 provides a binary code B₁, B₂, . . . , B_(i-1), B_(i),. . . , B_(n-1), B_(n) over a predetermined number of bits. Each bitB_(i) is provided on a terminal 3 ₁, 3 ₂, . . . , 3 _(i-1), 3 _(i), . .. , 3 _(n-1), 3 _(n) of circuit 1 which is specific to it. Circuit 1thus provides the binary code in parallel form.

[0030] According to the present invention, to each bit B_(i) of the codeis associated an electric path P₁, P₂, . . . , P_(i), . . . , P_(n)connecting common input terminal 2 to a terminal 3 _(i) of same rank.

[0031] It can thus already be seen that, by the different delaysintroduced by the electric paths, the edge triggering input signal E isreproduced on the different outputs at different times.

[0032] According to the present invention, it is provided to read theinformation present at the outputs of circuit 1 in a synchronized way.Preferably, a time approximately corresponding to an intermediary timebetween the shortest and longest delays introduced by the differentelectric paths is chosen.

[0033] More specifically, according to the preferred embodiment of thepresent invention illustrated in FIG. 1, an electric path 4 (C0) isprovided to set the read time from the occurrence of the edge triggeringinput signal E. This electric triggering path is chosen to introduce adelay included in the range of delays due to the paths providing thecode. It may for example be the average delay.

[0034] For example, path 4 connects input 2 of circuit 1 to theterminals Ck of flip-flops 5 ₁, 5 ₂, . . . , 5 _(i), . . . , 5 _(n)belonging to respective electric paths P₁, P₂, . . . , P_(i), . . . ,P_(n) and the respective Q outputs of which form output terminals 3 ₁, 3₂, . . . , 3 _(i), . . . , 3 _(n) of circuit 1. According to thisembodiment, each electric path P_(i) includes a delay element 6 ₁ (C1),6 ₂ (C2) . . . , 6 _(i) (Ci) . . . , 6 _(n) (Cn) connecting input 2 ofthe circuit to the D input of the corresponding flip-flop in the path.Delay elements 6 _(i) are the elements exhibiting, according to thepresent invention, different delays with respect to one another. Indeed,flip-flops 5 _(i) preferably have the same structure. They however takepart in the delay brought to the input signal until it reaches therespective output terminals of circuit 1 with respect to delay C0introduced by element 4.

[0035] When an edge is applied on input signal E, this edge reaches therespective D inputs of the flip-flops at different times. The reading ofthe input state of the different flip-flops is synchronized by the edgeof signal E delayed, this time, by element 4. For this reason, inparticular, a delay C0 approximately corresponding to the average delayof the different elements 6 _(i) is chosen.

[0036] In the example of FIG. 1, the different outputs 3 _(i) of circuit1 are individually connected at the input of a register 7 for storingthe obtained binary code, each bit B_(i) corresponding to one of thecircuit outputs. The connection and structure details of register 7 havenot been shown and are no object of the present invention. Once thebinary code is contained in this register, its exploitation depends onthe application, and its implementation is within the abilities of thoseskilled in the art.

[0037]FIGS. 2A and 2B illustrate, in the form of timing diagrams andwithout any scale consideration, the operation of a storage circuitaccording to the present invention. FIGS. 2A and 2B show examples ofshapes of signal E, and output signals of the different delay elements.In the example of FIGS. 2A and 2B, the case of a binary code over fourbits is considered. The timing diagrams have been designated withreferences C0, C1, C2, C3, and C4, respectively, C′0, C′1, C′2, C′3, andC′4 to illustrate that the delay elements are different therein.

[0038] The difference between FIGS. 2A and 2B represents the differencebetween two integrated circuits 1 having paths C0 to C4 introducingdifferent delays.

[0039] In FIG. 2A, it is assumed that at a time t5, a rising edge istriggered on signal E. This edge appears on the different inputs of theD flip-flops (corresponding to the outputs of delay elements C1, C2, C3,and C4) at different respective times t1, t2, t3, and t4. Further,element 4 (C0) introduces a delay starting the data reading at theflip-flop input at a time t0. All paths generating a delay greater thandelay C0 provide a bit at state 0 since the edge of signal E has notreached them yet. All paths generating a delay shorter than delay C0generate a bit at state 1 since the edge of signal E arrives on theinput of the corresponding flip-flop before delay C0 has expired. In theexample of FIG. 2A, at time t0, code 1010 is provided.

[0040]FIG. 2B illustrates a similar circuit in which paths C0′ to C4′are different. The code obtained therein is different. For example, itis code 0010. In FIG. 2B, a time t5 identical to the case of FIG. 1 hasarbitrarily been shown. However, times t′0, t′1, t′2, t′3, and t′4 atwhich the edge of signal E is at the end of its way through respectivepaths C′0, C′1, C′2, C′3, and C′4 are different from the case of FIG.2A.

[0041] Preferably, the delays introduced by the different paths arechosen to be sufficiently different from one another to by insensitiveto technological and manufacturing process dispersions. It is thusguaranteed that all the circuits in the same family do provide the samecode. Preferably, in the case of more than two paths, said paths aredifferent from one another even if they must provide the same result (0or 1). This makes a visual distinction between the paths even lessexploitable.

[0042] To provide a different code from one circuit to another, theelectric paths may be modified so that they introduce different delays,or the assigning of the different paths to the different flip-flops maybe modified, which modifies the order of the bits in the code. Averagedelay C0 may also be modified to shift the flip-flop triggering time. Inthis case, it will be ascertained to have all paths introducing delayswhich are, with respect to one another, independent from technologicalvariations.

[0043] According to an embodiment of the present invention, the code tobe stored is predetermined before the circuit manufacturing. In thiscase, delay elements C1 to Cn and/or element C0 are sized so that thecircuit provides this code.

[0044] According to another embodiment, the code is unknown upon designof the circuit. It is then identified after manufacturing by atriggering of the reading of the code of one of the circuits in thefamily. This code is common to all circuits in the family (manufacturedwith the same masks). It can thus be subsequently exploited, forexample, as a code of identification of the circuit type.

[0045] It may also be envisaged to individualize the codes of each chipon a same wafer, be it by individualizing the masks or the like, or byproviding delays sensitive to technological variations.

[0046] An advantage of the present invention is that the stored codecannot be visually detected. Indeed, for the code to appear, it isnecessary to apply an electric signal at the input of the circuit of thepresent invention.

[0047] Another advantage of the present invention is that it does notrequire organizing a read process to extract the code, as is the case ina conventional memory. According to the present invention, it issufficient to apply an edge on signal E to see the code appear on theoutput terminals, with a delay depending on the average delay. Cycletime of the system exploiting the integrated circuit is thus saved.

[0048] Another advantage of the present invention is that theidentification is particularly accurate and reliable. In particular, byeliminating the use of a measurement (memory reading), possible accuracyproblems are avoided.

[0049] Another advantage of the present invention is that the codeprovision is very fast. Indeed, manufacturing process or technologicalvariations most often introduce differences on the order of at most somehundred picoseconds. Accordingly, paths introducing delays in a range ofa few hundreds of picoseconds are sufficient to provide a code. The codeprovision time can thus be on the order of one nanosecond.

[0050] Another advantage of the present invention is that in case of adrift in time of one of the delays introduced by the elements, this doesnot alter the circuit results. Indeed, all delay elements beingpreferably of similar structure, the variation will be in the samedirection for all elements (paths).

[0051] To form the delay elements of the electric paths of the presentinvention, any integrated elements may be used. These may be, forexample, series of resistors and/or of capacitors, or mere tracks. Forthe resistors, resistors across the integrated circuit thickness may beused, but it will be preferred to use polysilicon resistors having avalue linked to the geometry and which have the advantage of being lesstemperature-dependent.

[0052] According to the present invention, a read phase is triggered byan edge of input signal E. The number of phases depends on theapplication and on the destination of the identification circuit. If itis a chip card, an identification upon each exchange performed betweenthis card and an external device may be provided, for example, evenduring the same transaction.

[0053] Of course, the present invention is likely to have variousalterations, modifications, and improvement which will readily occur tothose skilled in the art. In particular, the practical implementation ofthe delay elements of the present invention may take different forms.

[0054] Further, the choice of the variation range of the delaysintroduced by the different elements depends on the application and onthe desired sensitivity. This choice is within the abilities of thoseskilled in the art based on the functional indications given hereabove.

[0055] Further, it should be noted that the number of bits of the codeprovided by the circuit according to the present invention also dependson the application and on the desired degree of inviolability. Thehigher the number of bits, the more the distinction between two circuitsstoring different codes is made difficult.

[0056] Further, different elements of binary code exploitation uponcircuit use may be provided. Instead of being stored in a register, saidcode may, for example, be directly exploited to validate or invalidate afunction of the circuit in which it is integrated, for example, thesupply of this circuit.

[0057] Finally, although a preferred embodiment uses a single readtriggering signal E, several triggering signals may be provided,especially in the case of a circuit integrating several codes. In such acase, the different codes may or not share a same delay C0.

[0058] Among the applications of the present invention, it may beenvisaged to use the code as an identifier of the type of circuit for anautomated placing of the chips by a robot which previously identifiesthem by their code.

1. A circuit (1) for storing a binary code in an integrated circuitchip, characterized in that it includes: an input terminal (2) ofapplication of a signal (E) for triggering a reading of the code; outputterminals (3 ₁, 3 ₂, . . . , 3 _(i-l), 3 _(i), . . . , 3 _(n-l), 3 _(n))adapted to providing said binary code; first electric paths (P₁, P₂, . .. , P_(i), . . . P_(n)) individually connecting said input terminal toeach output terminal, each path introducing a delay set uponmanufacturing of the integrated circuit; and means (4, 5 ₁, 5 ₂, . . . ,5 _(i), . . . , 5 _(n)) for simultaneously taking into account binarystates present at the outputs of the electric paths.
 2. The circuit ofclaim 1, characterized in that each first electric path comprises adelay element (6 ₁, 6 ₂, . . . , 6 _(i), . . . , 6 _(n)) and of aflip-flop (5 ₁, 5 ₂, . . . , 5 _(i), . . . , 5 _(n)) having an inputterminal (D) connected at the output of the corresponding delay elementand having an output terminal (Q) defining one of the output terminalsof the circuit.
 3. The circuit of claim 1 or 2, characterized in thatsaid means for taking into account include a second electric path (4)introducing a delay (C0) included in the range of the delays introducedby said first paths, said second path being interposed between saidinput terminal (2) and a terminal for triggering the taking into accountof said binary states.
 4. The circuit of claims 2 and 3, characterizedin that each clock inputs (Ck) of the different flip-flops is connectedto said triggering terminal.
 5. The circuit of claim 3 or 4,characterized in that the first electric paths are chosen to introducedelays which remain shorter or longer than the delay of the second path(C0), despite possible technological dispersions.